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| 7A06L-101K资料 | |
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7A06L-101K PDF Download |
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File Size : 105 KB
Manufacturer:进口 Description: The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0] inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes valid. On the LOWCtoCHIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs prevent the LVCMOS compatible control inputs from floating. |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：7A06L-101K 厂 家：进口 封 装：贴片 批 号： 数 量：1645 说 明：1645 |
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运 费： 所在地： 新旧程度： |
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| 联系人：张伟升,张汉坤 |
| 电 话：0755-23816869 |
| 手 机：13480941178/13480639918 |
| QQ：949108432,695070213,799597862 |
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